The performance of a computer system can be enhanced by the use of a memory hierarchy. For example, a three tiered memory can be constructed from low, medium, and high speed memories. A low speed memory may be a magnetic disk for low cost, bulk storage of data. A medium speed memory may be constructed from DRAMs for use as the computer system's main memory. A high speed memory may employ SRAMs for use as a processor cache memory. The theory behind memory hierarchy is to group instructions and data to be executed by the system processor in the highest speed memory. Such high speed memory is typically the most expensive memory available, so economics dictate that it be relatively small. Main memory consisting of DRAMs is denser and less expensive than a cache memory with SRAMs, and can therefore be significantly larger than the cache memory.
During operation, the system processor transfers instructions and data from system memory to the cache memory in order to have quick access to the variables of the currently executing program. As additional data, not in the cache, is required, such data is transferred from the main memory by replacing selected data in the cache. Various techniques or algorithms are utilized to determine which data is replaced. Since the data in the cache is duplicative of data in the main memory, changes to data in one memory must similarly be changed or noted in the other memory. The problem of maintaining consistency between the cache and main memory data is referred to as coherency. For example, if the data in the cache is modified, the corresponding data in the main memory must similarly be modified. A scheme for modifying data in the main memory at the same time as data in the cache is known as a write-through cache. Alternatively, if only the cache memory data is modified, then such modified cache data must overwrite the main memory data when it is replaced.
In many computer systems, typically large systems, the main memory may be accessed by devices other than the system processor. For example, data may be written to the main memory by another device while the processor is operating on data in its cache. If the data written to main memory overwrites data presently in the cache, a coherency problem is presented. In the past, a method such as bus snooping has been used. This involves monitoring a bus for writes to main memory and then checking a tag directory associated with the cache to see if the data is in the cache. If present, a flag is set in the cache tag directory to invalidate the entry so that the old data is not used by the processor. Since the processor is responsible for checking the cache tag directory, processing time is consumed. This problem is further exaggerated because multiple devices tend to primarily use their own areas of memory, so most writes to main memory from other devices will not affect the data presently in the processor cache. System performance deteriorates when the processor must take time to check the cache tag directory for data which is not presently residing therein.